View AT28HC256N-90JI_1213845.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Features
* Fast Read Access Time - 90 ns * Automatic Page Write Operation * * * * * * * *
- Internal Address and Data Latches for 64 Bytes - Internal Control Timer Fast Write Cycle Times - Page Write Cycle Time: 3 ms Maximum - 1 to 64-byte Page Write Operation Low Power Dissipation: 300 A Standby Current (CMOS) Hardware and Software Data Protection DATA Polling for End of Write Detection High Reliability CMOS Technology - Endurance: 105 Cycles - Data Retention: 10 Years Single 5V 10% Supply CMOS and TTL Compatible Inputs and Outputs JEDEC Approved Byte-wide Pinout
256 (32K x 8) High-speed Parallel EEPROM AT28HC256N
Description
The AT28HC256N is a high-performance electrically erasable and programmable read only memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmel's advanced nonvolatile CMOS technology, the AT28HC256N offers access times to 90 ns with power dissipation of just 440 mW. When the AT28HC256N is deselected, the standby current is less than 3 mA. The AT28HC256N is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the address and 1 to 64 bytes of data are internally latched, freeing the addresses and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA Polling of I/O7 . Once the end of a write cycle has been detected a new access for a read or write can begin. Atmel's AT28HC256N has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking.
LCC, PLCC Top View
A7 A12 A14 NC VCC WE A13 I/O1 I/O2 GND NC I/O3 I/O4 I/O5 14 15 16 17 18 19 20
Pin Configurations
Pin Name A0 - A14 CE OE WE I/O0 - I/O7 NC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect
A6 A5 A4 A3 A2 A1 A0 NC I/O0
5 6 7 8 9 10 11 12 13
4 3 2 1 32 31 30
29 28 27 26 25 24 23 22 21
A8 A9 A11 NC OE A10 CE I/O7 I/O6
3446B-PEEPR-4/04
Block Diagram
Absolute Maximum Ratings*
Temperature under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on OE and A9 with Respect to Ground ...................................-0.6V to +13.5V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
2
AT28HC256N
3446B-PEEPR-4/04
AT28HC256N
Device Operation
READ: The AT28HC256N is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their system. BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation. PAGE WRITE: The page write operation of the AT28HC256N allows 1 to 64 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 additional bytes. Each successive byte must be written within 150 s (tBLC) of the previous byte. If the tBLC limit is exceeded the AT28HC256N will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 - A14 inputs. That is, for each WE high to low transition during the page write operation, A6 - A14 must be the same. The A0 to A5 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. DATA POLLING: The AT28HC256N features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. TOGGLE BIT: In addition to DATA Polling the AT28HC256N provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Testing the toggle bit may begin at any time during the write cycle. DATA PROTECTION: If precautions are not taken, inadvertent writes to any 5-volt-only nonvolatile memory may occur during transition of the host system power supply. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes. HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the AT28HC256N in the following ways: (a) VCC sense - if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power-on delay - once VCC has reached 3.8V the device will automatically time out 5 ms typical) before allowing a write; (c) write inhibit - holding any one of OE low, CE high or WE high inhibits write cycles; and (d) noise filter - pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. SOFTWARE DATA PROTECTION: A software controlled data protection feature has been implemented on the AT28HC256N. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28HC256N is shipped from Atmel with SDP disabled.
3
3446B-PEEPR-4/04
SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to "Software Data Protection" algorithm). After writing the 3-byte command sequence and after tWC the entire AT28HC256N will be protected against inadvertent write operations. It should be noted, that once protected the host may still perform a byte or page write to the AT28HC256N. This is done by preceding the data to be written by the same 3-byte command sequence. Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP and SDP will protect the AT28HC256N during power-up and power-down conditions. All command sequences must conform to the page write timing specifications. It should also be noted that the data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation. After setting SDP, any attempt to write to the device without the three byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, read operations will effectively be polling operations. DEVICE IDENTIFICATION: An extra 64 bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12V 0.5V and using address locations 7FC0H to 7FFFH the additional bytes may be written to or read from in the same manner as the regular memory array. OPTIONAL CHIP ERASE MODE: The entire device can be erased using a 6-byte software code. Please see "Software Chip Erase" application note for details.
4
AT28HC256N
3446B-PEEPR-4/04
AT28HC256N
DC and AC Operating Range
AT28HC256N-90 Operating Industrial Temperature (Case) VCC Power Supply -40C - 85C 5V 10% AT28HC256N-12 -40C - 85C 5V 10%
Operating Modes
Mode Read Write
(2)
CE VIL VIL VIH X X X VIL
OE VIL VIH X
(1)
WE VIH VIL X VIH X X VIL
I/O DOUT DIN High Z
Standby/Write Inhibit Write Inhibit Write Inhibit Output Disable Chip Erase Notes: 1. X can be VIL or VIH. 2. Refer to AC programming waveforms. 3. VH = 12.0V 0.5V.
X VIL VIH VH
(3)
High Z High Z
DC Characteristics
Symbol ILI ILO ISB1 ISB2 ICC VIL VIH VOL VOH Parameter Input Load Current Output Leakage Current VCC Standby Current TTL VCC Standby Current CMOS VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 6.0 mA IOH = -4 mA 2.4 2.0 0.45 Condition VIN = 0V to VCC + 1V VI/O = 0V to VCC CE = 2.0V to VCC CE = VCC - 0.3V to VCC f = 5 MHz; IOUT = 0 mA Min Max 10 10 3 300 30 0.8 Units A A mA A mA V V V V
5
3446B-PEEPR-4/04
AC Read Characteristics
AT28C256N-90 Symbol tACC tCE
(1) (2)
AT28HC256N-12 Min Max 120 120 0 0 0 50 50 Units ns ns ns ns ns
Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first
Min
Max 90 90
tOE tDF
0 0 0
40 40
(3)(4)
tOH
AC Read Waveforms(1)(2)(3)(4)
tCE tOE tDF tACC tOH
Notes:
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T = 25C(1) Symbol CIN COUT Note: Typ 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V
1. This parameter is characterized and is not 100% tested.
6
AT28HC256N
3446B-PEEPR-4/04
AT28HC256N
AC Write Characteristics
Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tDV Notes: Parameter Address, OE Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Setup Time Data, OE Hold Time Time to Data Valid 1. NR = No Restriction. Min 0 50 0 0 100 50 0 NR
(1)
Max
Units ns ns ns ns ns ns ns
AC Write Waveforms
WE Controlled
tOES tOEH
tAS
tAH
tCH
tCS
tWPH tWP tDS tDH
CE Controlled
tOES tOEH
tAS
tAH
tCH
tCS
tWPH tWP tDV tDS tDH
7
3446B-PEEPR-4/04
Page Mode Write Characteristics
Symbol tWC tAS tAH tDS tDH tWP tBLC tWPH Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Pulse Width Byte Load Cycle Time Write Pulse Width High 50 0 50 50 0 100 150 Min Typ Max 3 Units ms ns ns ns ns ns s ns
Page Mode Write Waveforms(1)(2)
tWP tAS tAH tDH
tWPH
tBLC
tDS
tWC
Notes:
1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE). 2. OE must be high only when WE and CE are both low.
Chip Erase Waveforms
tS
tH
tS = tH = 5 s (min.) tW = 10 ms (min.)
tW
VH = 12.0V 0.5V
8
AT28HC256N
3446B-PEEPR-4/04
AT28HC256N
Software Data Protection Enable Algorithm(1)
LOAD DATA AA TO ADDRESS 5555
Software Data Protection Disable Algorithm(1)
LOAD DATA AA TO ADDRESS 5555
LOAD DATA 55 TO ADDRESS 2AAA
LOAD DATA 55 TO ADDRESS 2AAA
LOAD DATA A0 TO ADDRESS 5555
LOAD DATA 80 TO ADDRESS 5555
WRITES ENABLED(2)
LOAD DATA AA TO ADDRESS 5555
LOAD DATA XX TO ANY ADDRESS(4)
LOAD LAST BYTE TO LAST ADDRESS
LOAD DATA 55 TO ADDRESS 2AAA
ENTER DATA PROTECT STATE
Notes:
1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 64 bytes of data are loaded.
LOAD DATA 20 TO ADDRESS 5555
EXIT DATA PROTECT STATE(3)
LOAD DATA XX TO ANY ADDRESS(4)
LOAD LAST BYTE TO LAST ADDRESS
Software Protected Write Cycle Waveforms(1)(2)
tWP tAS tAH tDH
tWPH
tBLC
tDS
tWC
Notes:
1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE) after the software code has been entered. 2. OE must be high only when WE and CE are both low.
9
3446B-PEEPR-4/04
Data Polling Characteristics(1)
Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay
(2)
Min 0 0
Typ
Max
Units ns ns ns
Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See "AC Read Characteristics" on page 6.
0
ns
Data Polling Waveforms
tOEH tDH tOE tWR
Toggle Bit Characteristics(1)
Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See "AC Read Characteristics" on page 6.
(2)
Min 10 10
Typ
Max
Units ns ns ns
150 0
ns ns
Toggle Bit Waveforms
tOEH tOE tWR
tDH
Notes:
1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary.
10
AT28HC256N
3446B-PEEPR-4/04
AT28HC256N
Ordering Information(1)
tACC (ns) 90 120 Note: ICC (mA) Active 30 30 Standby 0.3 0.3 Ordering Code AT28HC256N-90JI AT28HC256N-12JI Package 32J 32J Operation Range Industrial (-40C to 85C) Industrial (-40C to 85C)
1. See "Valid Part Numbers" table below.
Package Type 32J 32-lead, Plastic J-leaded Chip Carrier (PLCC)
Valid Part Numbers
The following table lists standard Atmel products that can be ordered:
Device Numbers AT28HC256N AT28HC256N Speed 90 12 Package and Temperature Combinations JI JI
11
3446B-PEEPR-4/04
Packaging Information
32J - PLCC
1.14(0.045) X 45
PIN NO. 1 IDENTIFIER
1.14(0.045) X 45 0.318(0.0125) 0.191(0.0075)
E1 B
E
B1
E2
e D1 D A A2 A1
0.51(0.020)MAX 45 MAX (3X)
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL
D2
MIN 3.175 1.524 0.381 12.319 11.354 9.906 14.859 13.894 12.471 0.660 0.330
NOM - - - - - - - - - - - 1.270 TYP
MAX 3.556 2.413 - 12.573 11.506 10.922 15.113 14.046 13.487 0.813 0.533
NOTE
A A1 A2 D D1 D2
Note 2
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum.
E E1 E2 B B1 e
Note 2
10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 32J REV. B
R
12
AT28HC256N
3446B-PEEPR-4/04
Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759
Regional Headquarters
Europe
Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500
Microcontrollers
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60
Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80
Asia
Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743
Japan
9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Literature Requests
www.atmel.com/literature
Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems.
(c) Atmel Corporation 2004. All rights reserved. Atmel (R) and combinations thereof, are the registered trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others.
Printed on recycled paper.
3446B-PEEPR-4/04

▲Up To Search▲

Price & Availability of AT28HC256N-90JI

	To Download AT28HC256N-90JI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .